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Prof. Pionteck

Prof. Dr.-Ing. Thilo Pionteck

Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl Hardware-nahe Technische Informatik
Universitätsplatz 2, 39106, Magdeburg, Gebäude 09, Raum 317
Tel.: +49 (391) 67 57148
Fax: +49 (391) 67 11237

Prof. Dr.-Ing. Thilo Pionteck

Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl Hardware-nahe Technische Informatik
Universitätsplatz 2, 39106, Magdeburg, Gebäude 09, Raum 317
Tel.: +49 (391) 67 57148
Fax: +49 (391) 67 11237
Projekte
Publikationen

2017

Begutachteter Zeitschriftenartikel
Werner, Stefan;  Heinrich, Dennis;  Groppe, Sven;  Pionteck, Thilo 

Semi-static operator graphs for accelerated query execution on FPGAs
In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, 2017; http://dx.doi.org/10.1016/j.micpro.2017.07.010

2016

Begutachteter Zeitschriftenartikel
Joseph, Jan Moritz;  Blochwitz, Christopher;  García-Ortizc, Alberto;  Pionteck, Thilo 

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs
In: Microprocessors and microsystems. - Amsterdam [u.a.] : Elsevier, 2016

Werner, Stefan;  Heinrich, Dennis;  Groppe, Sven;  Blochwitz, Christopher;  Pionteck, Thilo 

Runtime adaptive hybrid query engine based on FPGAs
In: Open journal of databases : OJDB. - Lübeck : RonPub UG, Bd. 3.2016, 1, S. 21-41

Buchbeitrag
Joseph, Jan Moritz;  Wrieden, Sven;  Blochwitz, Christopher;  Garcia-Oritz, Alberto;  Pionteck, Thilo 

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip
In: 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc) : June 27-29, 2016, Tallinn, Estonia. - Piscataway, NJ : IEEE

Werner, S.;  Heinrich, D.;  Stelzner, M.;  Linnemann, V.;  Pionteck, T.;  Groppe, S. 

Accelerated join evaluation in Semantic Web databases by using FPGAs
In: Concurrency Computation, Vol. 28, 2016, Issue 7, S. 2031-2051, 10.1002/cpe.3502

Joseph, Jan Moritz;  Blochwitz, Christioher;  Pionteck, Thilo 

Adaptive allocation of default router paths in Network-on-Chips for latency reduction
In: 2016 International Conference on High Performance Computing & Simulation (HPCS). - Piscataway, NJ : IEEE

Backasch, R.;  Hempel, G.;  Blochwitz, C.;  Werner, S.;  Groppe, S.;  Pionteck, T. 

An architectural template for composing application specific datapaths at runtime
In: 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2016, 10.1109/ReConFig.2015.7393300

Blochwitz, C.;  Joseph, J.M.;  Backasch, R.;  Pionteck, T.;  Werner, S.;  Heinrich, D.;  Groppe, S. 

An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases
In: 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2016, 10.1109/ReConFig.2015.7393291

Joseph, Jan Moritz;  Winker, Tobias;  Ehlers, Christian;  Blochwitz, Christopher;  Pionteck, Thilo 

Hardware-accelerated pose estimation for embedded systems using vivado HLS
In: ReConFig : 2016 International Conference on Reconfigurable Computing and FPGAs : November 30 - December 2, Cancun, Mexico. - Piscataway, NJ : IEEE ; [Kongress: 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig, Cancun, Mexico, November 30 - December 2, 2016]

Herausgeberschaft
Hannig, Frank;  Cardoso, João M. P.;  Pionteck, Thilo;  Fey, Dietmar;  Schröder-Preikschat, Wolfgang;  Teich, Jürgen 

Architecture of Computing Systems – ARCS 2016
In: Vol. Architecture of Computing Systems ⿿ ARCS 2016, 2016, S. , ISSN 0302-9743, 10.1007/978-3-319-30695-7

2015

Begutachteter Zeitschriftenartikel
Raitza, M.;  Vogt, M.;  Hochberger, C.;  Pionteck, T. 

RAW 2014: Random number generators on FPGAS
In: ACM Transactions on Reconfigurable Technology and Systems, Vol. 9, 2015, Issue 2, 10.1145/2807699

Buchbeitrag
Joseph, J.M.;  Blochwitz, C.;  Pionteck, T.;  Garcia-Ortiz, A. 

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs
In: 2015 Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP and International Symposium on System-on-Chip, SoC 2015, 2015, 10.1109/NORCHIP.2015.7364370

Werner, S.S.;  Heinrich, D.;  Piper, J.;  Groppe, S.;  Backasch, R.;  Blochwitz, C.;  Pionteck, T. 

Automated composition and execution of hardware-Accelerated operator graphs
In: 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, ReCoSoC 2015, 2015, 10.1109/ReCoSoC.2015.7238078

Heinrich, D.;  Werner, S.;  Stelzner, M.;  Blochwitz, C.;  Pionteck, T.;  Groppe, S.T. 

Hybrid FPGA approach for a B+ tree in a Semantic Web database system
In: 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, ReCoSoC 2015, 2015, 10.1109/ReCoSoC.2015.7238093

2014

Buchbeitrag
Joseph, J.M.;  Pionteck, T. 

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling
In: 2014 International Symposium on System-on-Chip, SoC 2014, 2014, 10.1109/ISSOC.2014.6972440

Backasch, R.;  Hempel, G.;  Werner, S.;  Groppe, S.;  Pionteck, T. 

Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation
In: 2014 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2014, 2014, 10.1109/ReConFig.2014.7032533

Raitza, M.;  Vogt, M.;  Hochberger, C.;  Pionteck, T. 

Influence of magnetic fields and X-radiation on ring oscillators in FPGAs
In: Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS, 2014, S. 199-204, 10.1109/IPDPSW.2014.26

Werner, S.;  Heinrich, D.;  Stelzner, M.;  Groppe, S.;  Backasch, R.;  Pionteck, T. 

Parallel and pipelined filter operator for hardware-accelerated operator graphs in semantic web databases
In: Proceedings - 2014 IEEE International Conference on Computer and Information Technology, CIT 2014, 2014, S. 539-546, 10.1109/CIT.2014.162

2013

Buchbeitrag
Werner, S.;  Groppe, S.;  Linnemann, V.;  Pionteck, T. 

Hardware-accelerated join processing in large Semantic Web databases with FPGAs
In: Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013, 2013, S. 131-138, 10.1109/HPCSim.2013.6641403

Pionteck, T.;  Osterloh, C. 

Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems
In: Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013, 2013, S. 229-232, 10.1109/HPCSim.2013.6641419

Hempel, G.;  Hoyer, J.;  Pionteck, T.;  Hochberger, C. 

Register allocation for high-level synthesis of hardware accelerators targeting FPGAs
In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, 2013, 10.1109/ReCoSoC.2013.6581522

2012

Buchbeitrag
Hampel, V.;  Pionteck, T.;  Maehle, E. 

An approach for performance estimation of hybrid systems with FPGAs and GPUs as coprocessors
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 7179 LNCS, 2012, S. 160-171, 10.1007/978-3-642-28293-5_14

2011

Buchbeitrag
Pionteck, T.;  Osterloh, C.;  Albrecht, C. 

Linking formal description and simulation of runtime reconfigurable systems
In: Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, 2011, S. 158-163, 10.1109/ReConFig.2011.55

2010

Buchbeitrag
Pionteck, T.;  Brockmann, W. 

A concept of a trust management architecture to increase the robustness of nano age devices
In: Proceedings of the International Conference on Dependable Systems and Networks, 2010, S. 142-147, 10.1109/DSNW.2010.5542604

Pionteck, T.;  Osterloh, C.;  Albrecht, C. 

Latency reduction of selected data streams in network-on-chips for adaptive manycore systems
In: 28th Norchip Conference, NORCHIP 2010, 2010, 10.1109/NORCHIP.2010.5669432

Pionteck, T.;  Sammann, S.;  Albrecht, C. 

Optimizing runtime reconfiguration decisions
In: Proceedings - IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2010, 2010, S. 39-46, 10.1109/EUC.2010.16

Herausgeberschaft
Albrecht, C.;  Foag, J.;  Koch, R.;  Maehle, E.;  Pionteck, T. 

DynaCORE-dynamically reconfigurable coprocessor for network processors
In: Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, 2010, S. 335-354, 10.1007/978-90-481-3485-4_16

2009

Buchbeitrag
Albrecht, C.;  Koch, R.;  Pionteck, T. 

On the impact of buffer size on packet loss in adaptable network-on-chips for runtime reconfigurable system-on-chips
In: 2009 NORCHIP, 2009, 10.1109/NORCHP.2009.5397798

2008

Begutachteter Zeitschriftenartikel
Pionteck, T.;  Albrecht, C.;  Koch, R.;  Maehle, E. 

Adaptive communication architectures for runtime reconfigurable system-on-chips
In: Parallel Processing Letters, Vol. 18, 2008, Issue 2, S. 275-289, 10.1142/S0129626408003387

Buchbeitrag
Albrecht, C.;  Osterloh, C.;  Pionteck, T.;  Koch, R.;  Maehle, E. 

An application-oriented synthetic network traffic generator
In: Proceedings - 22nd European Conference on Modelling and Simulation, ECMS 2008, 2008, S. 299-305

Pionteck, T.;  Albrecht, C.;  Koch, R.;  Brix, T.;  Maehle, E. 

Design and simulation of runtime reconfigurable systems
In: Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, 2008, S. 154-157, 10.1109/DDECS.2008.4538776

Pionteck, T.;  Albrecht, C.;  Koch, R.;  Maehle, E. 

On the design parameters of runtime reconfigurable systems
In: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 2008, S. 683-686, 10.1109/FPL.2008.4630039

Albrecht, C.;  Roß, P.;  Koch, R.;  Pionteck, T.;  Maehle, E. 

Performance analysis of bus-based interconnects for a run-time reconfigurable co-processor platform
In: Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing, PDP 2008, 2008, S. 200-205, 10.1109/PDP.2008.52

Pionteck, T.;  Koch, R.;  Albrecht, C.;  Maehle, E.;  Meitinger, M.;  Ohlendorf, R.;  Wild, T.;  Herkersdorf, A. 

SPP1148 booth: Network processors
In: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 2008, S. 352, 10.1109/FPL.2008.4629960

Albrecht, C.;  Koch, R.;  Pionteck, T.;  Maehle, E.;  Werner, M.;  Fuchsen, R. 

WCET determination tool for embedded systems software
In: SIMUTools 2008 - 1st International ICST Conference on Simulation Tools and Techniques for Communications, Networks and Systems, 2008, 10.4108/ICST.SIMUTOOLS2008.3044

2007

Buchbeitrag
Koch, R.;  Pionteck, T.;  Albrecht, C.;  Maehle, E. 

A lightweight framework for runtime reconfigurable system prototyping
In: Proceedings of the International Workshop on Rapid System Prototyping, 2007, S. 61-64, 10.1109/RSP.2007.7

Pionteck, T.;  Albrecht, C.;  Koch, R.;  Maehle, E.;  Hübner, M.;  Becker, J. 

Communication architectures for dynamically reconfigurable FPGA designs
In: Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM, 2007, 10.1109/IPDPS.2007.370364

Albrecht, C.;  Pionteck, T.;  Koch, R.;  Maehle, E. 

Modelling tile-based run-time reconfigurable systems using SystemC
In: 21st European Conference on Modelling and Simulation: Simulations in United Europe, ECMS 2007, 2007, S. 509-514

Pionteck, T.;  Stiefmeier, T.;  Staake, T.;  Glesner, M. 

On the design of a dynamically reconfigurable function-unit for error detection and correction
In: IFIP International Federation for Information Processing, Vol. 240, 2007, S. 283-297, 10.1007/978-0-387-73661-7_18

Pionteck, T. 

Teaching informatics students the secrets of hardware design
In: Proceedings - MSE 2007: 2007 IEEE International Conference on Microelectronic Systems Education: Educating Systems Designers for the Global Economy and a Secure World, 2007, S. 31-32, 10.1109/MSE.2007.82

2006

Begutachteter Zeitschriftenartikel
Pionteck, T.;  Kabulepa, L.D.;  Glesner, M. 

Exploring the capabilities of reconfigurable hardware for OFDM-based wlans
In: IFIP International Federation for Information Processing, Vol. 200, 2006, S. 149-164, 10.1007/0-387-33403-3_10

Buchbeitrag
Pionteck, T.;  Albrecht, C.;  Koch, R. 

A dynamically reconfigurable packet-switched network-on-chip
In: Proceedings -Design, Automation and Test in Europe, DATE, Vol. 1, 2006

Koch, R.;  Pionteck, T.;  Albrecht, C.;  Maehle, E. 

An adaptive system-on-chip for network applications
In: 20th International Parallel and Distributed Processing Symposium, IPDPS 2006, Vol. 2006, 2006, 10.1109/IPDPS.2006.1639445

Pionteck, T.;  Koch, R.;  Albrecht, C. 

Applying partial reconfiguration to networks-on-chips
In: Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, 2006, S. 155-160, 10.1109/FPL.2006.311208

2005

Buchbeitrag
Glesner, M.;  Hinkelmann, H.;  Hollstein, T.;  Indrusiak, L.S.;  Murgan, T.;  Obeid, A.M.;  Petrov, M.;  Pionteck, T.;  Zipf, P. 

Reconfigurable embedded systems: An application-oriented perspective on architectures and design techniques
In: Lecture Notes in Computer Science, Vol. 3553, 2005, S. 12-21

2004

Buchbeitrag
Pionteck, T.;  Stiefmeier, T.;  Staake, T.R.;  Glesner, M. 

A dynamically reconfigurable function-unit for error detection and correction in mobile terminals
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 3203, 2004, S. 1090-1092

Pionteck, T.;  Staake, T.;  Stiefmeier, T.;  Kabulepa, L.D.;  Glesner, M. 

Design of a reconfigurable AES encryption/decryption engine for mobile terminals
In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 2004, S. II545-II548

Glesner, M.;  Hollstein, T.;  Indrusiak, L.S.;  Zipf, P.;  Pionteck, T.;  Petrov, M.;  Zimmer, H.;  Murgan, T. 

Reconfigurable platforms for ubiquitous computing
In: 2004 Computing Frontiers Conference, 2004, S. 377-389

2003

Begutachteter Zeitschriftenartikel
Pionteck, T.;  Kabulepa, L.D.;  Glesner, M. 

On the Rapid Prototyping of Equalizers for OFDM Systems
In: Design Automation for Embedded Systems, Vol. 8, 2003, Issue 4, S. 283-295, 10.1023/B:DAEM.0000013063.88613.e0

Buchbeitrag
Pionteck, T.;  García, A.;  Kabulepa, L.D.;  Glesner, M. 

Hardware evaluation of low power communication mechanisms for transport-triggered architectures
In: Proceedings of the International Workshop on Rapid System Prototyping, Vol. 2003-January, 2003, S. 141-147, 10.1109/IWRSP.2003.1207041

Pionteck, T.;  Kabulepa, L.D.;  Schlachta, C.;  Glesner, M. 

Reconfiguration requirements for high speed wireless communication systems
In: Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003, 2003, S. 118-125, 10.1109/FPT.2003.1275739

2002

Buchbeitrag
Pionteck, T.;  Zipf, P.;  Kabulepa, L.D.;  Glesner, M. 

A framework for teaching (re)configurable architectures in student projects
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2438 LNCS, 2002, S. 444-451

Pionteck, T.;  Toender, N.;  Kabulepa, L.D.;  Glesner, M.;  Kella, T. 

On the rapid prototyping of equalizers for OFDM systems
In: Proceedings of the International Workshop on Rapid System Prototyping, Vol. 2002-January, 2002, S. 48-52, 10.1109/IWRSP.2002.1029737

2001

Buchbeitrag
Becker, J.;  Pionteck, T.;  Habermann, C.;  Glesner, M. 

Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture
In: Proceedings - IEEE Computer Society Workshop on VLSI, WVLSI 2001, 2001, S. 41-46, 10.1109/IWV.2001.923138

Becker, J.;  Liebau, N.;  Pionteck, T.;  Glesner, M. 

Efficient mapping of pre-synthesized IP-cores onto dynamically reconfigurable array architectures
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2147, 2001, S. 584-589

Kabulepa, L.D.;  Kella, T.;  Pionteck, T.;  Ludewig, R.;  Becker, J.;  Plechinger, J.;  Glesner, M. 

On the numerical accuracy of cordic-based frequency offset compensation in burst oriented OFDM systems
In: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Vol. 2, 2001, S. 1069-1072

Herausgeberschaft
Becker, J.;  Pionteck, T.;  Glesner, M. 

Effiziente IP-basierte abbildungsverfahren für dynamisch rekonfigurierbare array-architekturen
In: ITG-Fachbericht, 2001, Issue 164, S. 315

2000

Buchbeitrag
Becker, J.;  Pionteck, T.;  Glesner, M. 

An application-tailored dynamically reconfigurable hardware architecture for digital baseband processing
In: Proceedings - 13th Symposium on Integrated Circuits and Systems Design, 2000, S. 341-346, 10.1109/SBCCI.2000.876052

Becker, J.;  Pionteck, T.;  Glesne, M. 

DReAM: A dynamically reconfigurable architecture for future mobile communication applications
In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 1896, 2000, S. 312-321

Kooperationen
  • Otto-von-Guericke-Univeristät Magdeburg, Prof. Gunter Saake
  • Universität Bremen, Prof. Alberto Garcia-Ortiz
  • Privatdozent Dr. Sven Groppe, Universität zu Lübeck
Profil
Service
  • Entwurfsraumexploration für kombinierte Hardware-/Softwaresysteme
  • Entwurf und FPGA-Prototyping digitaler Schaltungen
Vita
Presse

Letzte Änderung: 28.08.2017 - Ansprechpartner:

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